1. Field of the Invention
The present invention relates to a semiconductor memory, which has a single transistor provided between embedded diffusion layers of two transistors in a memory cell so as to separate elements of the embedded diffusion layers, and a manufacturing method thereof. The present invention particularly relates to a semiconductor memory, which achieves the coexistence of the above element separation and insulating element separation, and a manufacturing method thereof.
2. Description of the Related Art
A semiconductor memory known as a representative semiconductor device is broadly divided into a volatile memory, in which stored information is erased when the power is turned off, and a nonvolatile memory, in which stored information is kept even when the power is turned off. The former is known as a random access memory (RAM) and the latter is known as a read only memory (ROM).
Of the above semiconductor memories, the ROM has been particularly adopted for a variety of information processing devices because of its nonvolatile characteristic. Above all, an EP (Erasable and Programmable) ROM and an EEP (Electrically Erasable and Programmable) ROM have been widely used. In the EPROM, written information can be erased by ultraviolet radiation and information can be electrically written again. In the EEPROM, information can be electrically erased and then written. A type of the EEPROM in which information can be erased at once and information can be written on a byte-by-bite basis has been known as a flash memory and has attracted attention as a replacement for a conventionally representative storage medium such as a floppy disk and a hard disk.
Each of these writable nonvolatile semiconductor memories has an MIS (Metal Insulator Semiconductor) structure. In this structure, a metal gate has a laminated structure having a floating gate embedded into an insulating film and a control gate being disposed above the floating gate via the insulating film. Electric charge is applied to the floating gate, which is electrically insulated from the surroundings, so as to store information. The accumulated electric charge is held in the floating gate even when the power is turned off, so that a nonvolatile function is achieved.
For example, Japanese Patent Laid-open Publication No. Hei. 6-283721 discloses the above-mentioned nonvolatile semiconductor memory, in which embedded diffusion layers are formed on semiconductor regions at both sides of a floating gate and the embedded diffusion layers are used as bit lines, and a manufacturing method thereof. FIG. 1 is a plan view showing the structure of a conventional nonvolatile semiconductor memory disclosed in Japanese Patent Laid-open Publication No. Hei. 6-283721. FIG. 2 is a sectional view taken along Exe2x80x94E line shown in FIG. 1.
As shown in FIGS. 1 and 2, in the conventional nonvolatile semiconductor memory, a first floating gate 54 and a second floating gate 55 are provided in parallel with each other via a gate oxide film 53 on a region such as an active region surrounded by element separating oxide films 52. The element separating oxide films 52 are formed at the surface of a P-type semiconductor substrate 51. N-type drain regions 56 and 57 are formed respectively between the element separating oxide films 52 and the first and second floating gates 54 and 55 at the surface of the semiconductor substrate 51. Further, an N-type source region 58 is formed between the first and second floating gates 54 and 55 at the surface of the semiconductor substrate 51. A first memory transistor is composed of the first floating gate 54, the drain region 56, and the source region 58, and a second memory transistor is composed of the second floating gate 55, the drain region 57, and the source region 58. Namely, the source region 58 is shared by the first and second memory transistors.
The first and second floating gates 54 and 55 are covered with an insulating film 60, which is composed of a laminated film so-called ONO (Oxide-Nitride-Oxide) including a silicon oxide film, a silicon nitride film, and a silicon oxide film. Control gates 61 are provided on the first and second floating gates 54 and 55 via the insulating film 60. Generally, polycrystalline silicon is used as the first and second floating gates 54 and 55 and the control gates 61.
As shown in FIG. 1, in the above construction of the nonvolatile semiconductor memory, the regions 56, 57, and 58 serve as embedded diffusion layers and extend to the adjacent memory cell as bit lines. Meanwhile, the control gates 61 extend along its length in a substantially perpendicular direction to the length of the regions 56, 57, and 58, and the control gates 61 are used as word lines.
Referring to FIGS. 3A to 3E, hereinafter a manufacturing method of the conventional nonvolatile semiconductor memory will be described in order of steps.
First, as shown in FIG. 3A, an oxidation resistance mask film 63 composed of a silicon nitride film is formed using the P-type semiconductor substrate 51 on a part serving as an active region, via a buffer film 62 composed of a silicon oxide film. Then, oxidation is performed by well-known LOCOS (Local Oxidation of Silicon) method so as to form the element separating oxide films 52 serving as field oxide films.
Next, after the buffer film 62 and the oxidation resistance mask film 63 are removed, as shown in FIG. 3B, normal oxidation is performed so as to form the gate oxide film 53 at the surface of the active region. Subsequently, with CVD (Chemical Vapor Deposition) method, a first conductive layer 64 made of polycrystalline silicon is entirely formed. Then, as shown in FIG. 3C, while resist films 65 cover regions on which the floating gates of the first conductive layer 64 are formed by photolithography method, the first conductive layer 64 is patterned so as to form the first floating gate 54 and the second floating gate 55, which are in parallel with each other. When the first and second floating gates 54 and 55 are formed by patterning the first conductive layer 64, mask alignment (position alignment) is performed in photolithography method. The mask alignment uses as a reference position the previously formed element separating oxide films 52 or a position alignment pattern, which is formed simultaneously with the above step.
Subsequently, an N-type impurity such as arsenic is ionically implanted into the active region by self-alignment using the resist films 65 and the first and second floating gates 54 and 55 as a mask. Afterwards, as shown in FIG. 3D, a heating operation is performed so as to form the N-type drain regions 56 and 57 and the source region 58. The regions 56, 57, and 58 are used as embedded diffusion layers. And then, oxidation is performed after the heating operation so as to increasingly oxidize the surfaces of the regions 56, 57, and 58, where N-type impurities are doped in a high concentration. Thus, an oxide film 66 is formed with a larger thickness than the gate oxide film 53. Therefore, the drain regions 56 and 57 and the source region 58 are embedded by the oxide film 66 and are used as embedded diffusion layers.
Next, as shown in FIG. 3E, with CVD method, the insulating film 60 composed of an ONO film is formed for covering the floating gates and covers the first and second floating gates 54 and 55. Afterwards, a second conductive layer 67 made of polycrystalline silicon is entirely formed thereon with CVD method, and the second conductive layer 67 is patterned so as to form the control gate 61, thereby completing the nonvolatile semiconductor memory shown in FIGS. 1 and 2.
Incidentally, in the manufacturing method of the conventional nonvolatile semiconductor memory disclosed in the above publication, when forming the floating gates by patterning the conductive layer, it is inevitable that displacement (misalignment) occurs relative to the element separating oxide film, which is a reference position of photolithography. Hence, the embedded diffusion layers, which are formed at both ends of the floating gate after this step, differ from each other in width on the right and left sides of the floating gate.
Namely, in the manufacturing method of the conventional nonvolatile semiconductor memory shown in FIGS. 3A to 3E, when the first conductive layer 64 is patterned so as to form the first and second floating gates 54 and 55, it is necessary to previously form the resist films 65 serving as masks on the first conductive layer 64. For this reason, a mask for forming a resist pattern is used with the element separating oxide film 52 and the like serving as a reference position to perform alignment on the semiconductor substrate 51.
However, in mask alignment, an exposing apparatus has a limit of mechanical accuracy of positioning, so that misalignment is inevitable. Therefore, especially in the recent lithography technique demanding fine patterning, accuracy of processing is seriously affected. For example, in the step illustrated in FIG. 3C, the resist films 65 are slightly shifted from predetermined positions to the right or left due to misalignment. Thus, the drain regions 56 and 57 and the source region 58, which are formed by self-alignment using the resist films 65 as a mask, differ from one another in width. Hereinafter, the drain regions 56 and 57 and the source region 58 will be collectively called embedded diffusion layers.
Hence, the embedded diffusion layers 56, 57, and 58, which serve as bit lines at both ends of the first and second floating gates 54 and 55, differ from one another in width. Uneven widths of the embedded diffusion layers result in uneven resistances thereof, so that a readout current of the nonvolatile semiconductor memory becomes irregular, causing a reading error. Particularly in the case of a nonvolatile semiconductor memory having a multilevel function of determining three or more kinds of current and reading current as data, slight irregularity of a readout current is likely to cause a reading error. Especially in finer patterning, a resistance value of an embedded diffusion layer is increased, so that a difference is reduced from an on-state resistance of a memory cell. Hence, reading determination with a sense amplifier is more difficult. For this reason, a margin has been conventionally provided for a width of the embedded diffusion layer in the design, in order to reduce a resistance value of the embedded diffusion layer to a certain value or less even when the embedded diffusion layers differ from one another in width in the manufacturing process. Consequently, it has been difficult to reduce the chip size.
The above misalignment also affects a nonvolatile semiconductor memory shown in FIG. 4, in which a single floating gate 68 is provided and embedded diffusion layers are provided at both ends thereof.
An object of the present invention is to provide a semiconductor memory and a manufacturing method thereof, by which it is possible to eliminate unevenness in width of the embedded diffusion layers respectively provided at both ends of a floating gate, the unevenness being resulted from misalignment.
According to one aspect of the present invention, a semiconductor memory comprises a memory cell region and a peripheral circuit region. The memory cell region includes semiconductor memory cells arranged in an array, and element separating shield electrodes which extend in a column direction and separate semiconductor memory cells being adjacent to each other in a row direction. The peripheral circuit region includes a peripheral circuit sending and receiving data to and from the semiconductor memory cell, and an element separation insulating film which separate elements in the peripheral circuit, the element separating shield electrodes extending onto the element separation insulating film at a boundary between the memory cell region and the peripheral circuit region.
According to the aspect of the present invention, element separation between the semiconductor memory cells is performed by the element separating shield electrodes, so that no misalignment occurs in the manufacturing process. Therefore, it is not necessary to provide a margin which has been conventionally required for misalignment on a diffusion layer. Hence, the memory cell region can be reduced. Additionally, the element separating shield electrodes extend onto the element separation insulating films at the boundary between the memory cell region and the peripheral circuit region. Thus, even when a contact hole reaching the element separating shield electrode is formed by plasma etching in the manufacturing process, it is possible to prevent plasma irradiation from causing dielectric breakdown on a thin insulating film, thereby securing high reliability.
According to another aspect of the present invention, a manufacturing method of the semiconductor memory comprises the steps of forming a gate conductive layer on a semiconductor substrate, and forming a source diffusion layer and a drain diffusion layer of the semiconductor memory cell by ion implantation into the semiconductor substrate using the gate conductive layer as a mask. All gate electrodes of the semiconductor memory cell and all of the element separating shield electrodes are integrated on the gate conductive layer.
According to the manufacturing method, the above misalignment can be eliminated, so that it is not necessary to provide a margin, which has been conventionally required for misalignment on the diffusion layer. Thus, the memory cell region can be reduced.
The manufacturing method preferably comprises the step of forming the element separation insulating film for the peripheral circuit, before forming the gate conductive layer. In element separation of the peripheral circuit, it is difficult to separate elements by the element separating shield electrodes. Hence, an ordinary method such as LOCOS method, recess LOCOS method, and trench insulating separation may be adopted, thereby readily manufacturing the element separating insulation film even in the case of a complex form.
Moreover, the shield electrodes may extend onto the element separation insulating films so as to eliminate a region having no element separation. Also, element separation can be readily switched just by overlapping. If the shield electrodes and the element separation insulating films are separated from each other, an electrically inseparable region exists between the cell region and the peripheral circuit region, so that some signals may cause a short.
Additionally, the step of forming the gate conductive layer is preferably a step of extending parts serving as the element separating shield electrodes of the gate conductive layer onto the element separation insulating film at a boundary between the memory cell region and the peripheral circuit region. In case that the element separating shield electrodes extend onto the element separation insulating film at the boundary between the memory cell region and the peripheral circuit region, when a contact hole reaching the element separating shield electrode is formed thereafter by plasma etching, it is possible to prevent plasma irradiation from causing dielectric breakdown on the thin insulating film, thereby securing high reliability.
Furthermore, the manufacturing method may further comprises the steps of, forming an interlayer insulating film at least in the memory cell region, forming a contact hole reaching the element separating shield electrode on a region where the element separating shield electrodes and the element separation insulating film overlap each other in the interlayer insulating film, embedding a conductive layer into the contact hole, and forming a metal layer on the interlayer insulating film, the metal layer being connected to a well on which the memory cells are formed, so that the conductive layer is connected to the well via the metal layer. In this case, a metal wire serving as a main source line can be adopted, so that it is not necessary to provide another region for a contact hole and the like. Therefore, it is preferable for saving an area.